Design requirements for ESD protection structures in CMOS circuits


Electrostatic discharge can have devastating consequences for electronic devices, and it is one of the main causes of integrated circuit failure. With the continuous development of integrated circuit technology, the feature size of CMOS circuits is shrinking, the gate oxide thickness of tubes is getting thinner and thinner, the area of ​​chips is getting larger and larger, and the current and voltage that MOS tubes can withstand are getting smaller and smaller. The peripheral environment has not changed, so to further optimize the circuit's anti-ESD performance, how to make the full chip effective area as small as possible, ESD performance reliability meets the requirements and no additional process steps need to be added to become the main consideration for IC designers. .

ESD protection principle

The ESD protection circuit is designed to prevent the working circuit from being damaged by the ESD discharge path, ensuring that the ESD occurring between any two chip pins has a suitable low-resistance bypass to introduce the ESD current into the power line. This low-resistance bypass not only needs to absorb the ESD current, but also clamps the voltage of the working circuit to prevent the working circuit from being damaged due to voltage overload. When the circuit works normally, the antistatic structure does not work. This makes the ESD protection circuit also need to have good working stability and can respond quickly when ESD occurs. While protecting the circuit, the antistatic structure itself cannot be damaged. The negative effects of the antistatic structure (such as input delay) must be within acceptable limits and prevent latch-up of the antistatic structure.

Design of CMOS circuit ESD protection structure

Most of the ESD current comes from outside the circuit, so the ESD protection circuit is typically designed next to the PAD, inside the I/O circuit. A typical I/O circuit consists of an output driver and an input receiver. ESD is imported into the chip through the PAD. Therefore, all devices directly connected to the PAD in the I/O need to establish a parallel ESD low-resistance bypass, which introduces the ESD current into the voltage line, and then distributes the voltage line to each pin of the chip. Reduce the impact of ESD. Specific to the I / O circuit, is the output drive and input receiver connected to the PAD, must ensure that when the ESD occurs, form a low-impedance path parallel to the protection circuit, bypass the ESD current, and can effectively clamp the protection circuit immediately Voltage. When these two parts work normally, it does not affect the normal operation of the circuit.

Commonly used ESD protection devices are resistors, diodes, bipolar transistors, MOS tubes, thyristors, and the like. Since the MOS tube has good compatibility with the CMOS process, the MOS tube is often used to construct the protection circuit.

The NMOS transistor under CMOS process has a lateral parasitic npn (source-p-substrate-drain) transistor that absorbs a large amount of current when turned on. This phenomenon can be used to design a protection circuit with a high ESD withstand voltage in a small area. The most typical device structure is the gate grounded NMOS (GGNMOS, GateGrounded NMOS).

Under normal operating conditions, the NMOS lateral transistors will not turn on. When ESD occurs, the drain and the depletion region of the substrate will avalanche, accompanied by the generation of electron-hole pairs. A portion of the generated holes are absorbed by the source and the rest flow through the substrate. The substrate voltage is increased due to the presence of the substrate resistance Rsub. When the PN junction between the substrate and the source is positively biased, electrons are emitted from the source into the substrate. These electrons are accelerated by the electric field between the source and the drain, generating collisional ionization of electrons and holes, thereby forming more electron-hole pairs, increasing the current flowing through the npn transistor, and finally causing the NMOS transistor to occur. After the breakdown, the breakdown at this time is no longer reversible, and the NMOS transistor is damaged.

To further reduce the voltage across the NMOS at the ESD of the output driver, a resistor can be added between the ESD protection device and the GGNMOS. This resistor does not affect the operating signal and therefore cannot be too large. Polysilicon (poly) resistors are often used to draw layouts.

With only one level of ESD protection, the tube inside the circuit is likely to be broken down during large ESD currents. GGNMOS is turned on. Since the ESD current is very large, the resistance of the substrate and the metal connection line cannot be ignored. At this time, the GGNMOS cannot clamp the gate voltage of the input receiving terminal because the voltage of the gate silicon oxide layer of the input receiving terminal is hit. The voltage across is the IR drop between the GGNMOS and the input receiving substrate. To avoid this, a small size GGNMOS can be added near the input receiving terminal for secondary ESD protection, which is used to clamp the input and receiving terminal gate voltage, as shown in Figure 1.

Common ESD protection structure and equivalent circuit

Figure 1 Common ESD protection structure and equivalent circuit

When drawing a layout, care must be taken to place the secondary ESD protection circuit close to the input receiver to reduce the resistance of the substrate and its wiring between the input receiver and the secondary ESD protection circuit. In order to draw a large-sized NMOS tube in a small area, it is often drawn as a finger in the layout, and the layout rules should be strictly followed by the I/OESD design rules.

If the PAD is only used as an output, the protection resistor and the short-grounded NMOS of the gate are not needed. The large-size PMOS and NMOS devices of the output stage can be used as ESD protection devices. Generally, the output stage has a double protection ring. Prevent latch-up from occurring.

When designing a full-chip ESD structure, be aware of the following principles:

(1) The peripheral VDD and VSS traces are as wide as possible, reducing the resistance on the trace;

(2) Design a voltage clamping structure between VDD and VSS, and provide a VDD-VSS direct low impedance current bleeder channel when ESD occurs. For larger circuits, it is best to place one such structure around the chip. If possible, placing multiple VDD and VSS PADs on the periphery of the chip can also enhance the ESD resistance of the overall circuit.

(3) The power supply and ground trace of the peripheral protection structure should be separated from the internal trace as much as possible. The peripheral ESD protection structure should be designed as evenly as possible to avoid the ESD weak link in the layout design;

(4) The design of the ESD protection structure should be balanced in consideration of the ESD performance of the circuit, the chip area, and the influence of the protection structure on the circuit characteristics such as input signal integrity, circuit speed, and output drive capability. To optimize the circuit design;

(5) In some circuits actually designed, sometimes there is no direct VDD-VSS voltage clamp protection structure. At this time, the voltage clamp between VDD-VSS and ESD current discharge mainly utilize the well of the whole circuit of the whole chip. The contact space of the substrate. Therefore, it is necessary to increase the contact of the well with the substrate as much as possible in the peripheral circuit, and the pitch of N+P+ is uniform. If there is space, it is better to add VDD-VSS voltage clamp protection structure beside and around the PAD of VDD and VSS. This not only enhances the anti-ESD capability in VDD-VSS mode, but also enhances I/OI/O mode. Anti-ESD capabilities.

Generally, as long as the above general principle is adopted, the anti-ESD voltage of a general sub-micron CMOS circuit can reach 2500V or more in consideration of the compromise of the chip area, which can meet the ESD reliability requirements of commercial civil circuit design.

For ESD structural design of deep submicron ultra-large-scale CMOS ICs, conventional ESD protection structures are usually no longer used. Usually, the Foundry production line, which is mostly deep sub-micron process, has its own external standard ESD structure, and has a strict standard ESD structure design. Rules, etc., the designer only needs to call its structure, which allows the chip designer to focus more on the design of the function and performance of the circuit itself.


ESD protection design is becoming more and more difficult with the improvement of CMOS technology level. ESD protection is not only the ESD protection design problem of input pins or output pins, but the electrostatic protection of all chips.

The corresponding ESD protection circuit needs to be established in every I/O circuit in the chip. In addition, the whole chip should be considered in its entirety. It is a good choice to use a whole-chip protection structure, and it can save I/OPAD. The area of ​​the ESD component.

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