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The new still image compression ISO/ITU-T standard JPEG2000 provides better coding performance than the previous JPEG standard. Based on the introduction of the ADV611 wavelet transform image compression chip, ADI first introduced the ADV202, a dedicated chip that implements the first part of the JPEG2000 standard. This paper presents a design scheme of JPEG2000 image compression and decompression system based on ADV202.
JPEG2000 image compression standard
JPEG2000 is an international standard for still image compression coding developed by the JPEG2000 Working Group. The standard number is ISO/IEC 15444|ITU-T T.800. The JPEG2000 standard, like other standards, consists of multiple parts. Among them, the first part is the core part of the code, which is open and free to use. It defines a set of lossless and lossy methods for the encoding of continuous tone, binary, grayscale or color still images. The other parts are the auxiliary and extension parts. The ADV202 supports all features of the first part except the ROI.
JPEG2000 uses many new compression coding techniques. First, the transform method uses Discrete Wavelet Transform (DWT). Second, embedded quantization is achieved by using a uniform quantizer with a central "dead zone". Third, context-based adaptive binary arithmetic coding is employed for each bit layer. Fourth, the optimized partitioned block coding (EBCOT) is used to obtain the best embedded code stream and improved error resistance. The structure of the JPEG2000 codec is shown in Figure 1.
Figure 1 JPEG2000 codec structure (a) encoder (b) decoder
JPEG2000 dedicated chip - ADV202
The ADV202 is a new ADI ASIC that implements the JPEG2000 codec. Figure 2 shows the structure of the ADV202. The ADV202 integrates a wavelet core based on the patented Space Efficient Recursive Filtering Wavelet Technology (SURFTM Wavelet Technology). This processor supports 9/7 and 5/3 wavelet transforms that achieve 6-layer decomposition. The ADV202's programmable block/image size is 2048 pixels wide in a three-component 4:2:2 interleaving mode. In single-component mode, the width can reach 4096 pixels. The maximum block/image height is 4096 pixels. The ADV202 also integrates an embedded 32-bit RISC processor. This processor is used to configure, control and manage the dedicated hardware inside the ADV202 and analyze/generate the JPEG2000 code stream that matches the user settings. Since entropy coding is the most computationally complex operation in the JPEG2000 compression/decompression process, three dedicated hardware entropy encoders are provided in the ADV202. The video interface of the ADV202 supports CCIR656, SMPTE125M PAL/NTSC, SMPTE293M [525p], TU.R-BT1358[625p] or any maximum input rate of 65 MSPS in irreversible mode and 40 MSPS in reversible mode. The ADV202's internal DMA engine provides high-speed data transfer between internal memories, internal memory, and individual functional blocks.
The ADV202 has two modes of operation, one is the encoding mode and the other is the decoding mode. In the encoding mode, the video data is input to the ADV 202 through the VDATA bus, the input data is wavelet-transformed by the wavelet check, and the wavelet coefficients of all frequency sub-bands are stored in the internal memory of the ADV 202. Each subband is further divided into code sub-blocks according to the setting of the ADV202 coding parameters, and then the entropy coder performs content modeling and arithmetic coding on the coded sub-blocks, and the result of the operation is stored in the internal memory. It is then transferred by the internal DMA to the CODE FIFO, which outputs the compressed data stream to the ADV202 via the HDATA bus. In the decoding mode, the working process is the inverse of the encoding mode.
Figure 2 ADV202 structure diagram
The basic structure of the JPEG2000 compression subsystem is shown in Figure 3. It has four main parts. The video AD is performed by the ADV7189. The ADV7189 is a multi-format SDTV video decoder. It integrates a video decoder that automatically detects and converts standard analog baseband TV signals into 4:2:2 component digital video data conforming to CCIR601/CCIR656. As the backbone of the whole system, FPGA bridges the signals of each chip in the system and synthesizes some control signals. In the FPGA, the initial processing of the data and the channel coding can also be completed as needed. The DSP is the master of the system, which completes the initialization of the ADV202 and ADV7189. The DSP initializes the ADV202 through the data bus, and the initialization of the ADV7189 is performed through the I2C bus.
When the system starts working, the analog video signal captured by the camera is transmitted to the ADV7189. The ADV7189 is sampled and quantized to output the required digital video data. The video data stream is sent to the ADV202 for compression encoding via the bridge of the FPGA. In order to increase the compression ratio, the data stream can be lost during the streaming of the video data to artificially reduce the source data rate that needs to be compression encoded. The compressed data is then transmitted by the ADV 202 to the interface controller in the FPGA, and the controller outputs the compressed data stream according to the specified interface protocol.
Figure 3 JPEG2000 compression system structure
The basic structure of the JPEG2000 decompression subsystem is shown in Figure 4. It also has four main parts. The video DA is performed by the ADV7301. The ADV7301 is a multi-format SD, progressive/HDTV video encoder. It contains six high speed video D/A converters. In the decompression subsystem, the FPGA also bridges the signals of the various chips in the system. The DSP is the master of the system, which completes the initialization of the ADV202 and ADV7301.
After the system starts working, the compressed data stream is first received by the interface controller into the FIFO stored in the FPGA, and then the interface controller controls the received compressed data stream to be forwarded to the ADV 202 for decompression operation. When the input source video data is subjected to field loss processing in the compression subsystem, the decompression subsystem needs to perform field compensation processing. The digital video data output by the ADV202 is sent to the ADV7301 through the FPGA, and the ADV7301 performs video encoding to obtain an analog video signal. The analog video signal is played back by the monitor to obtain an image of the source.
Figure 4 JPEG2000 decompression system structure
There are two main parts of the system software: one is the execution program in the FPGA, and the other is the DSP program. Figure 5 shows the structure of the FPGA software module of the compression subsystem. The FPGA internal function module structure of the decompression subsystem and the compression subsystem is basically the same, and only needs to change the flow direction of the signal. Since the interface between the ADV202 and the DSP is not completely identical, the FPGA needs to complete the matching of some interface signals. The modules and timings in the FPGA are implemented using VERILOG HDL programming.
Figure 5 FPGA software module structure diagram of the compression system
In this system, the DSP is mainly responsible for the initialization of the chip. It does not participate in the codec process. After the DSP completes the initialization, it is in the state of waiting for processing interrupt. After the DSP responds to the interrupt, it can handle the abnormal event in time. The flowchart of the DSP main program is shown in Figure 6.
Figure 6 DSP main program flow chart
This paper proposes a design scheme of JPEG2000 image compression and decompression system based on ADV202. The system has great flexibility and scalability, and can develop a wide range of compression ratio changes with minimal modification of the design. Image compression system. Under the existing hardware conditions, image processing and image recognition programs can also be added to increase the application range of the system.
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