Frequency synthesis technology is a new technology in the development of modern radio technology, and it is also one of the key technologies in modern communication systems. It usually uses a crystal or a small number of crystals to form a standard frequency source, and then synthesizes various required frequencies. signal. These frequency signals have the same frequency stability and accuracy as standard frequency sources. A circuit constructed using this technique is referred to as a frequency synthesizer in a communication device. There are many types of frequency synthesizers, and digital frequency synthesizers are currently widely used. The digital frequency synthesizer consists of a crystal oscillator, a fixed frequency divider, a phase detector, a filter, and a VCO. The frequency signal outputted by the crystal oscillator is obtained by a fixed frequency divider to obtain a standard frequency, and the frequency signal output by the VCO is divided by a variable frequency divider to obtain an actual frequency signal, and the phase of the two signals is phase-compared in the phase detector. The path lock control voltage is applied to the VCO through a filter to control and correct the actual frequency signal until the loop is locked. When the required signal frequency is high, the design, fabrication and debugging of the circuit are difficult, and usually only rely on professional manufacturers to complete, not only high cost, but also a long production cycle. The TSA5526 chip is a general-purpose digital frequency synthesis integrated circuit introduced by Philips. It integrates crystal oscillator, fixed frequency divider, phase detector, filter and other circuits on one chip. The main characteristic parameters are as follows:
â— The frequency of the input RF signal is: 64 ~ 1300MHz;
â— The level of the input RF signal is: -28 ~ 3dBm;
â— Output error adjustment voltage is: 4.5 ~ 33V;
â—With lock detection function;
â— Built-in programmable 15bit crossover;
â— The reference signal division ratio can be selected in 512, 640, and 1024 by program control, and the frequency accuracy of 3.90625 kHz, 6.25 kHz, and 7.8125 kHz can be obtained when an external 4 MHz crystal oscillator is connected;
â—I2C bus and 3 bus can be selected for data transmission;
â— It is powered by a single power supply and has a power supply voltage of 4.5 to 5.5V.
2 pin function
The TSA5526 is available in SSOP16 and SO16 packages. The pinouts are shown in Figure 1. The function of each pin is listed in Table 1.
Table 1 Pin Functions of the TSA5526
|1||RF||RF signal RF input||Normally connected to the local oscillator output|
|3||VCC1||Power supply voltage 1||Chip power supply, connect +5V|
|4||VCC2||Power supply voltage 2||Switch control power supply, usually connected to +12V|
|5||BS4||Electronic switch BS4 output||PNP triode OC output|
|6||BS3||Electronic switch BS3 output||PNP triode OC output|
|7||BS2||Electronic switch BS2 output||PNP triode OC output|
|8||VS1||Electronic switch BS1 output||PNP triode OC output|
|9||CP||Loop filter||External RC filter network|
|10||Vtune||Error control voltage output||Output DC voltage through pull-up resistor and add to VCO|
|11||SW||Bus selector switch||I2C bus mode is selected when grounding; 3 bus mode is selected when floating|
|12||LOCK/ADC||Lock flag / ADC input||3 bus mode is the lock flag, active low; when I2C bus mode 5 is the level ADC input|
|13||SCL||Serial clock||Latch the data of the SDA output on the falling edge|
|14||SDA||Serial data||In the 3-bus mode, 18-bit, 19-bit and 27-bit data are available.|
|15||CE||Chip select signal||Active high|
|16||XTAL||Reference oscillation input||Usually external 4MHz crystal|
Table 2 Write Status Data Format
|Address byte (ADB)||1||1||0||0||0||MA1||MA0|
|Divided Byte (DI1)||0||N14||N13||N12||N11||N10||N9||N8|
|Frequency division byte 2 (DB2)||N7||N6||N5||N4||N3||N2||N1||N0|
|Control byte (CB)||1||CP||T2||T1||T0||RSA||RSB||0S|
|Electronic open byte (BB)||air||air||air||air||BS4||BS3||BS2||BS1|
3 internal structure and working principle
The internal structure block diagram of TSA5526 is shown in Figure 2. It consists of four parts: RF signal processing unit, reference signal processing unit, phase comparison and output unit, and interface control unit. The RF signal processing unit amplifies and divides the input RF small signal and divides it into a 15-bit programmable frequency divider. The size of the frequency division ratio can be determined according to the frequency of the input RF signal. The reference oscillator in the reference signal processing unit generates a reference signal through an external crystal while generating a reference signal via the reference frequency divider. The reference divider is programmable with three division ratios of 512, 640 and 1024. The two signals after frequency division are simultaneously applied to the digital phase comparator, and then the error control voltage output is obtained after passing through the charge pump, the amplifier and the driving transistor. The interface control unit is configured to implement communication between the microprocessor and the device. On the one hand, the data sent by the microprocessor is received and processed internally to form various control commands; on the other hand, the state of the device is sent to the microprocessor. . Through the different connections of the SW signal, two serial communication modes can be selected: I2C bus mode and 3 bus mode.
3.1 I2C bus mode
a. Write status? R/W=0?
In the write state, four data bytes are required to program the TSA5526, and the data byte should be sent to the chip after the address byte is transferred. When the address byte? first byte? is transmitted, the I2C bus sends and receives the address byte and the data byte, and the transfer is completed in one transmission. If the first data byte after the address byte is a divided byte or control byte, the chip will be partially programmed. Table 2 is the definition of its data bytes. In the table, MA1 and MA0 are programmable address bits that are used to control the voltage applied to the chip select. N14~N0 are programmable frequency division ratios, and the division ratio is:
CP is the control charge pump current level, CP is 0, the corresponding current is 60Î¼A, when CP is 1, the current is 280Î¼A? The default value?. T2 to T0 represent test bits. RSA and RSB select bits for the reference division ratio. 0S is the adjustable amplifier control bit. When the 0S bit is 0, the adjustable amplifier is turned on. The default value is 0. When the 0S bit is 1, it is turned off. BS4~BS1 are PNP electronic switch control bits, and the corresponding relationship is: when BSn is 0, the electronic switch n is turned on; when BSn is 1, the electronic switch n is turned off.
Table 3 read status data format
Table 4 3 bus mode data format
b. Read status? R/W=1?
Table 3 lists the read status data formats. When the auxiliary address bit is recognized, a response pulse is automatically generated to the SDA line. The data on the SDA line is valid when the SCL clock signal is high. The data byte is read from the device after the acknowledge signal is generated on the SDA line. If no main response signal is generated, the transfer process ends and the chip is released. The data line thus causes the microcontroller to generate a termination condition. When power-on, the POR flag is set to 1. When the data end flag is detected, the POR flag is reset and the end of the read cycle. FL is the entry latch flag that indicates when the loop is established. The cycle can be controlled by setting or clearing FL. ACPS is an automatic charging current conversion flag. When the automatic charging current conversion is turned on and the cycle is locked, this flag is 0, and the charging current is forced to be low. Under other conditions, ACPS is logic 1. In the I2C bus state, the built-in A/D converter converts the automatic frequency trimming analog level to digital and sends it to the microcontroller.
3.2 3 bus mode
In the 3-bus mode, the device receives data in 18 bits, 19 bits, and 27 bits, see Table 4. In this mode, when the chip select pin CE changes from low level to high level, the falling edge of the SCL pin input clock pulse will send the data on the SDA pin to the data register. The first four bits of the data are used. The on/off of the electronic switch is controlled. On the rising edge of the fifth clock pulse, the four bits of data are sent to the internal electronic switch control register. If an 18 or 19-bit data word is transmitted, the frequency bit will be sent to the frequency register when the level is switched from high to low on the chip select line. In the power-on reset state, the charge pump current is 280Î¼A, and the tuning voltage output is turned off. In the standard mode, when the ACPS flag is high, the test bits T2 to T0 are set to 001, and the TSA5526 output is disabled. . When a 27-bit data word is transmitted, the frequency bit will be sent to the frequency register when the 20th rising edge of the clock pulse arrives, and the control bit is switched from the high level to the low level on the chip select pin CE. When it is sent to the control register. In this mode, the reference division ratio is determined by the RSA and RSB bits. The test bits (T2, T1, T0), the charge pump control bit CP, the division ratio selection bits (RSA, RSB), and the 0S bit can only be performed. Bit transfer. Figure 3 shows the timing diagram for the 3-bus mode.
Table 5 Definition of 20H, 21H, 22H, 23H in RAM in AT89C51
The application circuit of TSA5526 in an avionics checker is shown in Figure 4. In the figure, the MCU and TSA5526 use the 3-bus mode for communication. P1.0 is connected to the SCL pin for serial clock output. P1.1 is connected to the SDA pin for serial data output. P1.2 is connected to the CE pin for chip selection control; the electronic switches BS1 to BS4 are used to generate four different frequency signals through the VCO, and the output of the VCO is sent to the RF pin of the TSA5526 through C6, and is divided by the frequency. The reference signal is phase compared. The error control voltage of the Vtune output is applied to the VCO via resistor R3 and capacitor C5. The values â€‹â€‹of R1 and C4 can be used to determine the speed of fine tuning. When the frequency is locked, the LOCK pin will go low and the level will be sent to the microcontroller through the P1.3 pin of the AT89C51 for detection. This circuit adopts the 27-bit data format, and the transmitted data is stored in the four units of 20H, 21H, 22H, and 23H of the RAM of the AT89C51 of the single-chip microcomputer. The definitions of each are listed in Table 5. The list of specific procedures is as follows:
Rfegadj: CLR P1.0
MOV R0, #08H
Fregadj1: MOV A, 20H
MOV P1.1, C
DJNZ R0, Fregadj1
Fregadj2: MOV A, 21H
MOV P1.1, C
DJNZ R0, Fregadj2
MOV R0, #08H
Fregadj3: MOV A, 22H
MOV P1.1, C
DJNZ R0, Fregadj3
MOV R0, #03H
Fregadj4: MOV A, 23H
MOV P1.1, C
DJNZ R0, Fregadj4
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